module encode_83 (
	input wire enable,
	input wire[7:0] data_in,
	output reg[2:0] data_out
	);
	integer i;
	
	always @(data_in or enable) begin
		if (enable == 1) begin
			for (i=0;i<8;i=i+1) begin
				if (data_in[i]==1)
					data_out=i;
			end
		end
	end
endmodule
